1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device, such as a semiconductor memory, which has a plurality of wires extending in parallel, and a method of manufacturing a semiconductor device of this type.
2. Description of the Related Art
In recent years, dynamic random-access memories (DRAMs) have had their integration density increased remarkably. There have been developed 16 M-bit DRAMs and 64 M-bit DRAMs. A DRAM having a storage capacity of 1 G bits, called "next-generation DRAM," is being developed now.
FIG. 1 is a plan view representing the layout pattern of a conventional DRAM or the like. As shown in FIG. 1, element regions 6 having source-drain contacts are arranged in parallel. Gate electrodes 3 are arranged to sandwich the element regions 6. Each of the gate electrodes 3 must be prevented from contacting with the contacts 7. For this reason, unnecessary spaces are created as shown in FIG. 1.
Meanwhile, a storage-node contact and a bit-line contact of a 16 M-bit DRAM or a 64 M-bit DRAM are formed using a hole pattern corresponding to one contact. If contacts of this type are formed in a 1 G-bit DRAM, each contact hole will have an insufficiently small area, because of the displacement of a contact-hole pattern with respect to the gate electrodes. As a consequence, contact failure may take place, as will be explained with reference to FIGS. 2A and 2B.
FIG. 2A and FIG. 2B are a plan view and a cross sectional view of a semiconductor device. As shown in FIGS. 2A and 2B, the device comprises a semiconductor substrate 1, a gate-insulating film 2, gate electrodes (wires) 3, a gate-protecting film 4, an inter-layer insulating film 5, an element region 6, and a contact 7. The inter-layer insulating film 5 is displaced with respect to the gate electrode 3 by the distance A. The contact holes inevitably have their area reduced to a value B which is less than the designed value.
As mentioned above, the greater the storage capacity of a DRAM, the less the area of each contact hole because of the displacement of the contact-hole pattern with respect to the gate electrodes. Consequently, contact failure will occur. This problem arises not only a DRAM, but also in semiconductor devices in which contact holes are provided among wires extending in parallel.